An FPGA based scheduling coprocessor for dynamic priority scheduling in hard real-time systems

Abstract

In this paper we present a scheduling coprocessor device for uniprocessor computer systems running a real-time operating system (RTOS). The coprocessor shortens the scheduling time of the operating system by performing dynamic priority computation for all tasks in parallel and making a task selection according to these priorities at a higher speed than a software solution would do. This paper starts with a survey of related work and gives a motivation for the development of the proposed coprocessor architecture. We describe the architecture of our deterministic scheduling coprocessor and an efficient FPGA implementation and give a performance evaluation.