A Survey on Design and Implementation of Floating Point Adder in FPGA

Abstract

FPGAs are widely being used in high performance and scientific computing applications. FPGAs are suitable for such applications when conventional processors implementations do not satisfy the realtime and high performance requirements. Most of these applications demand high numerical stability and accuracy, and wide range of numbers. Hence, they are usually based on floating point. Implementing floating point unit in FPGA is one of the crucial issues of hardware implementations. Floating point addition is the most frequent floating point operation and takes most of the scientific operation. It is a costly operation in terms of time and hardware. The main objectives of implementing floating point in FPGA are to achieve high performance with less area, increase the throughput, and decrease the latency. This review paper presents a survey on floating point addition algorithms and techniques, and the implementation of floating point adder in FPGA. © Springer International Publishing Switzerland 2015.