FPGA implementation of polar codes for low complexity decoder for high speed applications

Abstract

An emerging error-detection and correcting technique developed in the recent years is Polar codes. The technique does not focus on randomization of the bits like other techniques does, but is based on the Shannon theory and channel polarization. This paper presents a successive cancellation (SC) algorithm based FPGA implementation of Polar codes. The implementation focuses on low complexity decoder for high speed applications. Software Simulation outcomes represent the execution to polar codes can outperform those are turbo or LDPC codes.