Abstract
This paper describes the implementation of the L3 maze routing accelerator in an FPGA. L3 supports fast single-layer and multi-layer routing, preferential routing, and rip-up-and-reroute. A 16 X 16 single-layer and 4 X 4 multi-layer router that can handle 2-16 layers have been implemented in a low-end Xilinx XC2S300E FPGA. Larger arrays are currently under construction. © Springer-Verlag Berlin Heidelberg 2003.
Cite
CITATION STYLE
Nestor, J. A. (2003). FPGA implementation of a maze routing accelerator. Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 2778, 992–995. https://doi.org/10.1007/978-3-540-45234-8_103
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