Adaptive processors can exploit the different characteristics exhibited by program phases better than a fixed hardware. However, they may significantly degrade performance and/or energy consumption. In this paper, we describe a reconfigurable cache memory, which is efficiently applied to the L1 data cache of an embedded general-purpose processor. A realistic hardware/software methodology of run-time tuning and reconfiguration of the cache is also proposed, which is based on a pattern-matching algorithm. It is used to identify the cache configuration and processor frequency when the programs data working-set changes. Considering a design scenario driven by the best product execution time×energy consumption, we show that power dissipation and energy consumption of a two-level cache hierarchy and the product timexenergy can be reduced on average by 39%, 38% and 37% respectively, when compared with a non-adaptive embedded microarchitecture. © Springer-Verlag Berlin Heidelberg 2006.
CITATION STYLE
Benitez, D., Moure, J. C., Rexachs, D. I., & Luque, E. (2006). A reconfigurable data cache for adaptive processors. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 3985 LNCS, pp. 230–242). Springer Verlag. https://doi.org/10.1007/11802839_31
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