Achieving Picosecond-Level Phase Stability in Timing Distribution Systems with Xilinx Ultrascale Transceivers

Abstract

This article discusses the challenges posed on the field-programmable gate array (FPGA) transceivers in terms of phase-determinism requirements for timing distribution at the Large Hadron Collider (LHC) experiments. Having a fixed phase after startups is a major requirement, and the typical phase variations observed in the order of tens of picoseconds after startups while using the state-of-the-art design techniques are no longer sufficient. Each limitation observed in the transmitter and receiver paths of the high-speed transceivers embedded in the Xilinx Ultrascale FPGA family is further investigated and solutions are proposed. Tests in hardware using Xilinx FPGA evaluation boards are presented. In addition to a higher phase determinism, the techniques presented make it possible to fine-tune the skew of a link with a picosecond resolution, greatly simplifying clock-domain crossing inside the FPGAs and providing better short-term stability for the FPGA-recovered clock in a high-speed link.