FPGA implementation of a novel type DDS based on CORDIC algorithm

Abstract

A novel digital frequency synthesizer (DDS) is introduced using CORDIC algorithm module instead of ROM look-up table module in the paper. Application of CORDIC algorithm module can greatly reduce the amount of storage and cancel the amount of storage to improve data accuracy and improve the DDS frequency resolution limits. An increasing zero-iteration of the CORDIC algorithm module is applied on a novel type DDS through the Altera FPGA chip using VerilogHDL programming. The simulation and verification results show the feasibility of this approach. This new method has simple circuit structure and high frequency resolution, suitable for VLSI inheritance compare with the old type DDS. © 2011 Springer-Verlag Berlin Heidelberg.