Topology-Aided Multicorner Timing Predictor for Wide Voltage Design

Abstract

In wide voltage design, timing needs to be verified at a very large number of corners. This article presents a learning-based approach to predict path timing for multiple unknown corners at low voltage, using long short-term memory (LSTM) to exploit circuit topology correlation with timing and a multigate mixture-of-experts (MMoE) network to capture correlation among all analysis corners. - Ulf Schlichtmann, Technical University of Munich.