Technology Characterization Model and Scaling for Energy Management

Abstract

We present a low-cost methodology to find the highest energy efficiency operating conditions (voltage and frequency) for a processor with given performance requirements. Taking a black box approach, we start with processor specifications: nominal voltage, clock frequency, thermal design power (TDP), maximum frequency and maximum power, and a knowledge of the device technology. To determine the behavior of the processor, we use a small model circuit that can be economically but accurately simulated in Spice to learn the delay and energy characteristics of the technology. We simulate the model with random vectors to determine power consumption profiles and critical path delays at several voltages. Comparisons between the model data and processor specifications provide scale factors for area, voltage, nominal frequency and maximum frequency. We then optimize the operating modes of the processor for highest cycle efficiency (clock cycles per unit energy). An illustration considers a processor with 3.3 GHz clock, 1.2 V nominal voltage, and 95 W thermal design power. Several optimization scenarios are possible. Observing that the clock is power constrained, we reduce the voltage to 0.92 V, keeping the clock at 3.3 GHz, which now becomes structure-constrained. This gives a 127% higher cycle efficiency over the nominal operation. For highest performance, we set the voltage to 1.1 V and increase the clock to 4.5 GHz while holding power unchanged at 95 W. This gives 38% higher cycle efficiency than the nominal operation. The highest cycle efficiency, ten times greater than the nominal, occurs for subthreshold voltage operation at 0.35 V and 36 MHz.