Analysis of equal and unequal transition time effects on power dissipation in coupled VLSI interconnects

Abstract

Packing more circuits on chip is achieved through aggressive device scaling and/or increase in chip size. This results in complex geometry of interconnect wires on-chip. High density chips have introduced problems like interconnect noise and power dissipation. The CMOS technology is best known for making ICs owing to its low power static dissipation and ease of integration when compared to BJT technology. As the CMOS technology moved below sub micron levels, the power consumption per unit chip area has increased manifolds. Low power consumption leads longer battery life and lesser heat generation in the circuit. The overall performance of a chip is largely dependent on interconnects. This paper addresses the impact of equal and unequal transition time of inputs on power consumption in coupled interconnects. To demonstrate the effects, a model of two distributed RLC lines coupled inductively and capacitively is considered. Each interconnect line is 4 mm long and terminated by capacitive load of 30 fF. The power dissipation is measured for dynamically switching inputs. © 2012 Springer-Verlag GmbH.