Qualitative optimization of coupling parasitics and driver width in global VLSI interconnects

Abstract

Analyses of the effects of interconnect wires in deep sub-micron technology is of prime importance in the modern era integrated circuits. The performance parameters such as crosstalk noise and delay are fundamentally dependent on interconnects and driver sizing. The coupling parasitics are the primary source of crosstalk. This paper addresses the optimization of coupling parasitics and driver sizing qualitatively for delay and peak noise. For this study, a pair of distributed RLC lines each of 4mm length is considered. These lines are coupled inductively and capacitively. The SPICE waveforms are generated at far end of lines for varying coupling parasitics and width of aggressor driver PMOS while keeping channel width of NMOS half of PMOS. The simulation is carried out at 0.13μm, 1.5 V technology node. Both the cases of simultaneous switching of inputs i.e in-phase and out-of-phase are taken into consideration. © Institute for Computer Sciences, Social Informatics and Telecommunications Engineering 2012.