FPGA based performance analysis of multistage CIC decimation filter design with former CIC filter for WIMAX applications

Abstract

The motto of this paper is to design and realize decimation filter using CIC filter. The main drawback of this filter is there is large droop in pass band and very less attenuation in stop band. So, to improve the frequency response of CIC filter we go for two stage realization of CIC filter. At the initial stage we use CIC filter and in the last stage we use Kaiser Window and improve the characteristics of filter design. When we design a filter using multistage methodology the order of the filter as well as power also decreases. Tools used are MATLAB Simulink Model and Xilinx system generator and realization is done on Virtex V-XC5VLX110T-3ff136. In this paper the proposed two stage realization is compared with respect to two stages Kaiser window realization in the terms of number of LUT’s required, slices as well as power dissipation and improvements in frequency response with respect to conventional CIC filter are compared.