The paper presents the design of a 60 GHz transceiver, with all active and passive devices integrated on-chip including the antenna, for multi Gbit short-range wireless communications. To minimize circuit complexity and cost an on-off-keying (OOK) modulation scheme is selected as well as a 65 nm bulk CMOS technology instead of more costly CMOS SOI or SiGe or III-V technologies. At transmitter side a differential 2 stage common source power amplifier allows for an output power of about 11 dBm. The receiver includes a cascode LNA with a gain of 11 dB and a noise figure of 4.6 dB, followed by a simple envelop detector. For the on-chip antenna, half-wavelength dipole and inverted-F topologies have been designed. For the transceiver prototype the half-wavelength dipole is selected since it has better gain performance (radiation efficiency of 38 %, a peak directivity of 1.76 and a gain of roughly −2 dBi) although for an higher area occupation. The fully integrated transceiver allows for a data rate of roughly 4 Gbit/s at distances of few meters, being compliant with physical-layer specifications of WirelessHD and WiGig alliances.
CITATION STYLE
Saponara, S., & Neri, B. (2016). Fully integrated 60 ghz transceiver for wireless hd/wigig short-range multi-gbit connections. Lecture Notes in Electrical Engineering, 351, 131–137. https://doi.org/10.1007/978-3-319-20227-3_17
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