Comparative Analysis of Vedic Multiplier using Various Adder Architectures

Abstract

The performance of a microprocessor depends on the efficient multiplier as it is one of the most principal component in various digital circuits. This paper reviews optimization techniques for high speed Vedic multiplier design which is based on Urdhva Tiryakbhyam Sutra of Ancient Indian Vedic Mathematics. This particular sutra is the most efficient one as it gives minimum delay for all types of complex multiplication. Adder being the most important component in a multiplier design, using the efficient adder will enhance the performance of Vedic multiplier. During the comparison, different adder topologies like Carry Look ahead Adder, Kogge Stone Adder, Carry Skip Adder are used to compare area, delay and power. The reviewed methods are implemented on 45nanometer(nm), 90nm and 180 nm CMOS technology. The results of all the prior approaches are reviewed and an efficient method out of them has been proposed.