A tile-based interconnect model for FPGA architecture exploration

Abstract

Modern FPGA has complex interconnect, like curve wires and two-level local muxs (global wires -> block input pins). Existing interconnect model (CB-SB) cannot describe these routing fabrics, hindering CAD exploration of modern FPGA. This paper presents INTB (Interconnect block) model to solve this problem. To represent all routing resources including curve wires and two-level local muxs, a five-side INTB is defined at each FPGA tile. Meanwhile, for simple description of large architecture space, hierarchical model parameters are designed. Besides, we modify CAD flow to apply INTB model: a memory-efficient method based on tile is adopted to generate routing resource graph (RRG); New strategies of routing cost estimation are used to route short and curve wires. INTB model and CAD modifications are implemented in VTR 8.0. The experiments include two parts: first, it is verified that our model is accurate and compatible with CB-SB model. The results show difference of switch area and timing between these two models is 1.21% and 1.11%. Second, our model is used to explore modern FPGA interconnect. Compared to original routing fabrics of VTR, curve wires reduce critical path delay by 11.77% and two-level local muxs reduce channel width by 17.36%.