Silicon and Germanium Junctionless Nanowire Transistors for Sensing and Digital Electronics Applications

Abstract

In this chapter, we introduce two specific types of junctionless nanowire transistors (JNTs): (i) silicon-on-insulator (SOI) back-gated JNTs for sensing applications and (ii) germanium-on-insulator (GeOI) top-gated JNTs for digital logic applications. We discuss in detail the suitability of junctionless architecture for these particular applications and present results on device fabrication and characterisation. Back-gated JNTs of 45 different channel geometries (different numbers, lengths, and widths of channel nanowires) have been designed and fabricated with very high precision (down to 10 nm widths of the nanowires) on SOI wafers using a fully CMOS-compatible fabrication process. Electrical characterisation of the fabricated devices has demonstrated their excellent performance as back-gated JNTs. Furthermore, data from pH and streptavidin sensing experiments have proven their good sensing properties. These JNTs are among the smallest top-down fabricated nanowire sensing devices reported to date. Top-gated JNTs with Ge nanowire channels of widths down to 20 nm have been fabricated by a simple CMOS-compatible process on GeOI wafers with a highly p-doped (~1×1019 cm−3) top germanium layer. The fabricated devices have demonstrated decent output and transfer characteristics with relatively high Ion/Ioff current ratios of up to 2.0 × 105 and steep subthreshold slopes of 189 mV/dec. To the best of our knowledge, these are the first reported Ge JNTs.