VLSI architectures for finding the first W maximum/minimum values are highly demanded in the fields of K-best MIMO detector, non-binary LDPC decoder and product-code decoder. In this paper, a VLSI architecture based on parallel comparing scheme is explored for finding the first W maximum/minimum values from M inputs. The place and route results using a TSMC 90-nm CMOS technology show that, despite some hardware cost, it achieves on average a 3.6x faster speed performance compared to the existing partial sorting architectures.
CITATION STYLE
Xiao, G., Ahmad, W., Zaidi, S. A. A., Roch, M. R., & Causapruno, G. (2016). High speed VLSI architecture for finding the first W maximum/minimum values. In Lecture Notes in Electrical Engineering (Vol. 351, pp. 35–41). Springer Verlag. https://doi.org/10.1007/978-3-319-20227-3_5
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