Comparison of low current mismatch CMOS charge pumps for analog PLLS using 180 nm technology

Abstract

We have reinvestigated the four different charge pumps (CPs) already reported in the literature and named them CP1, CP2, CP3 and CP4. These charge pumps are widely used in phase-locked loop (PLL) and have been compared for a number of parameters, mainly current mismatch, power consumption, voltage swing and the design complexity. We observed the current mismatch between the charging and discharging currents at control voltage of 0.9 V to be 3.88%, 2.7% and 3.55% for CP1, CP3 and CP4, respectively, while it is 6.96% for CP2 at control voltage of 1.3 V. At frequency of 50 MHz, CP4 consumes 377 µW power using 200 µA current source, CP3 consumes 1840 µW using 100 µA current source, CP1 consumes 704 µW using 80 µA current source, while CP2 consumes 756 µW power for bias voltage of 0.47 V. The voltage swing for CP1, CP2, CP3 and CP4 is obtained to be 0.2, 1.275, 0.9 and 0.3 V, respectively, at 50 MHz frequency.