TOC-BISR: A self-repair scheme for memories in embedded systems

Abstract

Memories are important components in embedded systems, since complex systems require more and more amount of data storage. Upcoming memories are more and more required to guarantee reliability for secure applications in the presence of massive soft and hard errors. This work proposes a fault tolerant customizable technique that combines EDAC, which can correct soft errors, and a built-in self-repair approach based on online testing and a Content Addressable Memory (CAM), which can tolerate hard errors. The goals of this approach are ensuring the correct operation of the system, extending the lifetime of the component, and improving the yield. This digital system was described in VHDL and synthesized in FPGA. The approach is customizable in terms of EDAC code, test algorithm and CAM size. The main advantage of the customization is to choose the best tradeoff between the number and type of tolerated and corrected errors compared to the area overhead and performance penalties for a target application.