Residue arithmetic for variation-tolerant design of multiply-add units

Abstract

This paper investigates the residue arithmetic as a solution for the design of variation-tolerant circuits. Motivated by the modular organization of residue processors, we comparatively study the sensitivity of residue arithmetic-based and binary processors to delay variations, and in particular the impact of delay variations onto the maximum critical path. Experiments are performed on two multiply-add (MAC) circuits based on residue and binary arithmetic. Results reveal that residue arithmetic-based circuits are up to 94% less sensitive to delay variation than binary circuits, thus leading to increased timing yield. © 2010 Springer Berlin Heidelberg.