Investigation of tunnel field-effect transistors as a capacitor-less memory cell

Abstract

In this work, we report experimental results on the use of tunnel field-effect transistors as capacitorless dynamic random access memory cells, implemented as double-gate fully depleted silicon-on-insulator devices. The devices have an asymmetric design, with a partial overlap of the top gate (LG) and with a total overlap of the back gate over the channel region (LG + LIN). A potential well is created by biasing the back gate (VBG) in accumulation, while the front gate (V FG) is in inversion. Holes from the p+ source are injected by the forward-biased p+ i junction and stored in the electrically induced potential well. © 2014 AIP Publishing LLC.