Electron multibeam technology for mask and wafer writing at 0.1 nm address grid

Abstract

- Abstract. IMS Nanofabrication realized a 50 keV electron multibeam proof-of-concept (POC) tool confirming writing principles with 0.1 nm address grid and lithography performance capability. The POC system achieves the predicted 5 nm 1 sigma blur across the 82 μm×82 μm array of 512×512 (262,144) programmable 20 nm beams. 24-nm half pitch (HP) has been demonstrated and complex patterns have been written in scanning stripe exposure mode. The first production worthy system for the 11-nm HP mask node is scheduled for 2014 (Alpha), 2015 (Beta), and first-generation high-volume manufacturing multibeam mask writer (MBMW) tools in 2016. In these MBMW systems the max beam current through the column is 1 μA. The new architecture has also the potential for 1× mask (master template) writing. Substantial further developments are needed for maskless e-beam direct write (EBDW) applications as a beam current of >2 mA is needed to achieve 100 wafer per hour industrial targets for 300 mm wafer size. Necessary productivity enhancements of more than three orders of magnitude are only possible by shrinking the multibeam optics such that 50 to 100 subcolumns can be placed on the area of a 300 mm wafer and by clustering 10 to 20 multicolumn tools. An overview of current EBDW efforts is provided.