A latency tolerant code generation algorithm for a coarse grain dataflow machine

Abstract

First, a specific coarse-grain dataflow architecture, the ADAMl-Architecture, is briefly introduced, highlighting the features which influence the language and compiler design of a high level language for this architecture. It is shown that the key requirement to hide latency leads to new code generation strategies. In the main part of the paper, an algorithm is presented to generate sequential codeblocks for the ADAM-Architecture from dataflow graphs. We prove that the demonstrated algorithm generates correct code. Comparing the codes generated from the new algorithm and from a traditional leftmost depth-first code generator, the tradeoff between number of used registers and gained concurrency is discussed. Finally, future research goals and the present state of work are demonstrated.