A reconfigurable multi-threaded architecture model

Abstract

Reconfigurable computing devices promise to deliver the performance of application-specific hardware along with the flexibility of general-purpose microprocessors. It is still a technology with confined dedications due to restricted hardware resources, high cost of developing and upgrading applications. Hardware virtualization with appropriate configuration techniques can be applied to significantly reduce these problems. This paper presents a novel architecture model for reconfigurable execution which virtualizes hardware resources to remove the fixed-size constraints present in conventional reconfigurable devices. The architecture maps computation threads via a pipelined configuration technique onto available physical hardware. Some application examples demonstrate that the proposed architecture concept provides performance and application flexibility. © Springer-Verlag Berlin Heidelberg 2003.