Power-efficient approach to optimize SHA-256 bit using reversible logic

Abstract

With the growing network to connect people all over the world, network security has received major attention in this field. Network security provides a secured way of communication eliminating unauthorized access and misuse of important data. Cryptography is the major entity of network security and involves conversion of readable data to apparent nonsense. Secured hash algorithm (SHA) is the family of cryptographic hash functions which are one-way faster with good security and consumes low power but they have attacks like brute-force attack, side-channel attack(particularly differential power analysis) and the main reason behind these power attack is power consumption. This paper is intended to implement SHA-2 design using reversible logic. Reversible logic has received great attention in low-power VLSI design, nanotechnology and quantum computing, etc. SHA-2 contains different length output hash functions which are 224, 256, 384 and 512 bits and are used in significant applications like digital signatures, authentication and message integrity checks. A novel approach in design of SHA-2 to achieve more security, less hardware and power consumption is minimized by using reversible logic. Proposed SHA-2 algorithm of 256 bits has been simulated using Xilinx through reversible logic. Proposed SHA-2 is power efficient and having less hardware complexity in comparison with existing work. Performance analysis of reversible implementation of SHA-2 with respect to gates used, garbage and quantum cost is done. Synthesis analysis of our work shows that total time delay is 626 ns and the final result shows 12% reduction in hardware requirements.