Highly compact automated implementation of linear CA on FPGAs

Abstract

The current literature on cellular automata (CA) mostly overlooks the fact that the perceived regularity and locality of interconnects in a CA are often logical rather than physical, and difficult to achieve in practical implementations. Optimized mapping, placement and routing of circuits are especially challenging for Field Programmable Gate Array (FPGA) platforms, which often result in low-performance implementations. We develop a design methodology for the automated implementation of low-resource, high-performance CA circuits, by optimal usage of the underlying FPGA architecture, direct primitive instantiation, and constrained placement. Case study for an 1-D CA circuit reveal higher performance, lower hardware resource requirement (by a factor of 0.5 X), acceptable power-delay product (PDP), and superior design scalability, in comparison to implementations derived by standard FPGA CAD tool design flow.