Reversible binary coded decimal adders using toffoli gates

Abstract

Reversibility plays a fundamental role when computations with minimal energy dissipation are considered. This research describes Toffoli Gate (TG) implementations of conventional Binary Coded Decimal (BCD) adders, adders for Quick Addition of Decimals (QAD), and carry select BCD adders suitable for multi-digit addition. For an N-digit fast adder, partial parallel processing is done on all digits in the decimal domain. Such high-speed BCD adders find application in realtime processors and internet-based computing. An analysis of delay normalized to a TG and quantum cost of BCD adders is presented. Implementations using TGs and Fredkin Gates (FRGs) are compared based on quantum cost, number of gates, garbage count and delay, and the results are tabulated. © Springer Science+Business Media B.V. 2009.