Reducing static energy of cache memories via prediction-table-less way prediction

Abstract

Power consumption is becoming one of the most important constraints for microprocessor design in nanometer-scale technologies. Especially, as the transistor supply voltage and threshold voltage are scaled down, leakage energy consumption is increased even when the transistor is not switching. This paper proposes a simple technique to reduce the static energy. The key idea of our approach is to allow the ways within a cache to be accessed at different speeds. We combine variable threshold voltage circuits with way prediction technique to activate only the way which will be referred, and propose a simple prediction mechanism which eliminates history tables. Experimental results on 32-way set-associative caches demonstrate that any severe increase in clock cycles to execute application programs is not observed and significant static energy reduction can be achieved, resulting in the improvement of energy-delay product. © Springer-Verlag Berlin Heidelberg 2003.