An Ultra Low Power AES Architecture for IoT

Abstract

Internet of Things (IoT) is now becoming a part of our life. Many devices are already connected, and more are expected to be deployed in the next coming years. The main concern for IoT is to provide a practical solution for security, privacy, and trust. The science of cryptography plays an important role for providing security in IoTs. AES algorithm is a well known symmetric key, block cipher that is highly secure. In this paper, we present an ultra-low power architecture for the AES cipher that is need for most IoT applications. The proposed architecture has been implemented on SCL 180 nm technology. We have used 4-bit serializer and deserializer (SerDes) to send and receive 128-bit data. The proposed AES architecture uses 32-bit data path in SubByte transformation, and it requires 44 clock cycles for encryption of 128-bit plaintext with a 128-bit cipher key. To deserialize 128-bit plaintext and cipher key, the architecture requires 32 clock cycles. Similarly, to serialize 128-bit ciphertext, 32 clock cycles are overlapped by 44 clock cycles required by AES module. By this, once, after the first 32 clock cycles, the use of SerDes does not affect on the throughput of the system. At 10 MHz the ASIC implementation of the proposed architecture on SCL 180 nm PDK consumes 52.2 µ W and 194.7 µ W power at 1 V and 1.8 V respectively and provides a throughput of 28 Mbps.