This paper presents an efficient architecture for computing cryptographic ηT pairing for providing 128-bit security. A cryptoprocessor is proposed for Miller's Algorithm with a new 1223-bit Karatsuba multiplier that exploits parallelism. To the best of our knowledge this is the first hardware implementation of 128-bit secure ηT pairing on supersingular elliptic curves over characteristic two fields. The design has been implemented on Xilinx FPGAs. The place-and-route results show that the proposed design takes only 190 μs to complete an 128-bit secure ηT pairing on a Virtex-6 FPGA. The proposed cryptoprocessor achieves eight times speedup compared to the best known existing design. It also outperforms the previous designs with respect to area x time product. © 2011 International Association for Cryptologic Research.
CITATION STYLE
Ghosh, S., Roychowdhury, D., & Das, A. (2011). High speed cryptoprocessor for ηT pairing on 128-bit secure supersingular elliptic curves over characteristic two fields. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 6917 LNCS, pp. 442–458). https://doi.org/10.1007/978-3-642-23951-9_29
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