Investigation of junctionless transistor based dram

Abstract

In this work, we have investigated Double Gate junctionless transistor based capacitorless Dynamic Random Access Memory (1T-DRAM). The back gate is responsible for formation of an electrostatic potential well, while the front gate distinguishes the two states based on the charge stored at the back. The read operation is performed through drift-diffusion mechanism. The independent gate operation results in a retention time of 170 ms for gate length of 400 nm at 85 °C.