The shared cache structures and snoop cache structures for single-chip multiprocessors are evaluated and compared using an instruction level simulator. Simulation results show that 1-port large shared cache achieves the best performance if there is no delay penalty for arbitration and accessing the bus. However, if 1-clock delay is assumed for accessing the shared cache, a snoop cache with internal wide bus and invalidate style NewKeio protocol overcomes shared caches.
CITATION STYLE
Kisuki, T., Wakabayashi, M., Yamamoto, J., Inoue, K., & Amano, H. (1997). Shared vs. Snoop: Evaluation of cache structure for single-chip multiprocessors. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 1300 LNCS, pp. 793–797). Springer Verlag. https://doi.org/10.1007/bfb0002815
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