FPGA Implementation of Binary Morphological Processing for Image Feature Extraction

Abstract

The present digital world requires the need for image feature extraction from images, videos, moving object etc in the applications of medical, surveillances, authentication and automated industry inspection. The image extraction can be performed by using different digital techniques like image segmentation, image enhancement, image analysis, image restoration, image representation, image description and morphological techniques. The mathematical morphology is a process of accepting image pixel values and performing algorithmic computations like dilation, erosion, opening and closing etc. The mathematical morphology can be designed and implemented by using software, Digital Signal Processing (DSP) and FPGA/ASIC. The Software and DSP implementations are slow in operation and cannot be used for high speed applications. Hence, FPGA implementation can be used for high speed applications. The proposed design accepts an input image from a video/ photo and converts into image pixels matrix. This image pixel array matrix of [255*255] is structured with structuring element of [3*3] array matrix for the mathematical morphology feature extraction. The selection of structuring element is based on the type of shapes of an image. The proposed system is designed by using Verilog HDL, MATLAB software and implemented using Xilinx-System Generator, Xilinx ISE design tools and targeted for Spartan-3E-XC3E-500-4FG320 FPGA board.