Comparative analysis of D flip-flops in terms of delay and its variability

Abstract

There is vast variation encountered in present circuits because of aggressive scaling and process imperfections. So this paper deals with various D flip-flop circuits in terms of robustness and propagation delay. This work compares various known D flip-flop circuits and then identifies the circuit which is fastest as compared to others taken into consideration. Further, delay variability exhibited by circuits has been analyzed to test the immunity against PVT variations i.e. process, voltage and temperature. In this paper, we have investigated the output levels of various D flip-flop circuits. Push-pull isolation D flip-flop proves to be more efficient as compared to other circuits in terms of delay variability. The circuits have been simulated using 32-nm technology node on SPICE. The designs offering minimum delay and its variability are reported, to aid the designer in selecting the best design depending on specific requirements.