Switching noise optimization in the wake-up phase of leakage-aware power gating structures

Abstract

Leakage power dissipation has become a critical issue in advanced pro cess technologies. The use of techniques to reduce leakage power consumption with negligible degradation in performances is needed for current and next tech nologies. Power gating is an effective technique to reduce leakage, taking advantage of the transistor stacking effect. However, the restoration from standby mode in power-gated circuits usually introduces a large amount of switching noise on the power supply and ground networks, that may affect the normal operation of circuits connected to the same polarizations. This paper analyzes the switching noise generated in the wake-up phase by several power-gat ing techniques, and their influence on the wake-up time. The best results are for the techniques that redistribute the amount of current flowing through the Vdd and Gnd nodes during the wake-up transition. Simulation results obtained on basic digital cells in a 90 nm technology show a variation of two in switching noise, while maintaining the same wake-up time and leakage saving. © 2010 Springer Berlin Heidelberg.