A novel bulk drain connected 6T SRAM cell

Abstract

Static Random Access Memory (SRAM) being the fastest on chip memory is scaled everyday making a challenge to reduce the leakage current and to sustain its consistency. This paper focuses on the six transistor (6T) realization of the SRAM cell. Two existing SRAM architectures are analyzed and their drawbacks in the deep submicron regions are identified. A novel bulk-drain connected architecture of a six transistor (6T) SRAM cell is proposed. The proposed structure exhibits the capability of minimizing the leakage current in deep submicron region and at the same time maintaining the optimum hold and read noise margins. The performance of the proposed circuit is compared with the conventional 6T SRAM cell using a PTM 32 nm CMOS technology parameters. It is found that the proposed cell structure reduces the leakage current by 44% in comparison to conventional SRAM architecture.