IP ware for neural networks

Abstract

In order to fill the gap between the increasing silicon capability available to IC designers new design methodologies, based on reusable Intellectual Property (IP) cores, are being developed. This evolution of circuit design has led us to investigate the casting of Artificial Neural Networks (ANNs) into a form suitable for use as IP ware. The Modular Map design is a fully digital implementation of an ANN. It was first implemented using a combination of different design techniques in a 0.65 μm process.Then a new model in the form of a Register Transfer Level (RTL) synthesisable VHDL description suitable for IPware applications has been developed. This paper will present a comparison of the original implementation of a single neuron in the Modular Map design and a fully synthesised version targeted towards a number of standard cell technologies. Each neuron contains a small local register file which has been implemented using synthesised VHDL, synthesis tool supplied generators, and where available full custom generators. Area performance data for these will be given. Casting of the design to a parameterised form suitable for a variety of ANN application areas will also be discussed.