Performance sensor for reliable operation

Abstract

Human-Computer Interaction (HCI) applications need reliable hardware and the development of today’s sensors and cyber-physical systems for HCI applications is critical. Moreover, such hardware is becoming more and more self-powered, and mobile devices are today important devices for HCI applications. While battery-operated devices quest for the never-ending battery, aggressive low-power techniques are used in today’s hardware systems to accomplish such mission. Techniques like Dynamic Voltage and Frequency Scaling (DVFS) and the use of subthreshold power-supply voltages can effectively achieve substantial power savings. However, working at reduced power-supply voltages, and reduced clock frequency, imposes additional challenges in the design and operation of devices. Today’s chips face several parametric variations, such as PVTA (Process, power-supply Voltage, Temperature and Aging) variation, which can affect circuit performance and reliability is affected. This paper presents a performance sensor solution to be used in cyber-physical systems to improve reliability of today’s chips, guaranteeing an error-free operation, even with the use of aggressive low-power techniques. In fact, this performance sensor allows optimize the trade-off between power and performance, avoiding the occurrence of errors. In order to be easily used and adopted by industry, the performance sensor is a non-intrusive global sensor, which uses two dummy critical paths to sense performance for the power-supply voltage and clock frequency used, and for the existing PVTA variation. The novelty of this solution is on the new architecture for the sensor, which allows the operation at VDDs’ subthreshold voltage levels. This feature makes this global sensor a unique solution to control DVFS, even at subthreshold voltages, avoid performance errors and allow optimizing circuit operation and performance. Simulations using a SPICE tool allowed characterizing the new sensor to work at sub-threshold voltages, and results are presented for a 65 nm CMOS technology, which uses a CMOS Predictive Technology Models (PTM) technology. The results show that the sensor increases sensibility when PVTA degradations increase, even when working at subthreshold voltages.