FPLD HDL synthesis employing high-level evolutionary algorithm optimisation

Abstract

This paper presents a novel approach to optimising high level designs for circuits to be implemented on FPLDs. The aim is to search the design space using an evolutionary algorithm to find solutions that optimise circuit speed and circuit size under given constraints. To ensure correct circuit operation, a library of synchronous functional modules are used and interchanged in the circuit, altering only each module’s data type (not its functionality). After modifying a circuit, modules for data synchronising and type conversions are added automatically. It is these extra modules that cause the search to become non-linear, indicating that the combination of optimised sub-circuits does not necessarily give an overall optimised circuit. The input to the synthesiser and optimiser is a netlist of modules, while the output is a completely specified Altera Hardware Description Language (AHDL) listing ready to be compiled. The main advantages of the method are that existing sub-circuits can be utilised, circuits can often be fit into available hardware without being redesigned, advances in algorithms and sub-circuit designs can be utilised, and low-level compilers and optimisers are left to their speciality.