Light-weight fine-grain dynamic partial reconfiguration on xilinx FPGAs

Abstract

In this paper, we propose novel light-weight fine-grain dynamic and partial reconfiguration (DPR) methods on Xilinx FPGAs, where bit-streams for look-up table (LUT) reconfiguration can be generated on-demand on the FPGA without using FPGA design tools, aiming at enabling more flexible DPR on FPGAs. Although the methods only focus on reconfiguration of LUTs, reconfiguration time of 2.4 to 5.2 μ s can be achieved including the preparation time of configuration data with compact controllers. Power consumption of reconfiguration is as low as in the normal operation, suggesting effectiveness of the proposed DPR methods in terms of power-performance ratio.