Design of Bit Parallel Multiplier with Lower Time Complexity

Abstract

Recently efficient implementation of finite field operations has received a lot of attention. Among GF(2m) arithmetic operations, a multiplication process is the most basic and a critical operation that determines a speed-up in hardware. Mastrovito multipliers using a trinomial p(x) = xm + xn + I(n m/2) require m2 - 1 XOR gates and m2 AND gates. The proposed multiplier that depends on the intermediate term xn needs m2 AND gates and m2 + (n2 - 3n)/2 XOR gates. The time complexity of existing multipliers is TA + ([(m -2)/(m - n)] + 1 + [log2m]) Tx ([12]) and that of the proposed method is TA + (1 + [log2(m -1 + [n/2)])]) TX. The proposed architecture is efficient for the extension degree m suggested as standards: SEC2, ANSI X9.63. In average, the space complexity is increased to 1.18% but the time complexity is reduced 9.036%. © Springer-Verlag 2004.