Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation

Abstract

An efficient algorithm is presented which accounts for series resistance by computing a reduced-order approximation for the driving-point admittance of an RC tree. The algorithm consists of four rules which allow the Taylor series expansion coefficients of the driving-point admittance looking downstream of a given point in the tree to be correctly propagated further upstream. Rules 1-3 involve movement upstream, along a single branch, and past, respectively, a lumped capacitor to ground, a series lumped resistor, and a uniformly distributed RC segment. Rule 4 involves combining two or more different admittance expansions in parallel at a branch point in the tree. Using an emiter-coupled-logic clock buffer as an example, the authors demonstrate a significant improvement in accuracy.