A coarse-grain dynamically reconfigurable system and compilation framework

Abstract

Traditionally, there have been two classes of computing: general-purpose systems and application-specific embedded systems. The former is based on the usage of general-purpose processors wherein a single processor is used to execute a variety of applications. The latter category is based on the use of application specific integrated circuits (ICs) or ASICs, each of which is custom designed for a specific application. However, there is also a third class of computing, reconfigurable computing, which has recently come forth into prominence. Reconfigurable computing refers to computing systems that have reconfigurable architectures or are based on reconfigurable hardware components. The underlying principle of these systems is that the hardware organization, functionality or interconnections may be customized after fabrication of the system on silicon. This customization helps satisfy specific computational requirements of different applications. A reconfigurable architecture or a system consisting of reconfigurable devices exhibits the following features: • Configurable functionality: This implies that the processing unit can execute different functions at different times based on different configuration information. • Configurable interconnect: This refers to the ability of the interconnections to be changed to meet different communication patterns or other application constraints. • Configurable Storage: This indicates that the storage mechanisms (e.g. memories) inside the reconfigurable system can be changed in structure or functionality in order to best suit the data movements for a given application. • Configurable I/O: This refers to the ability of the system to change the bitwidth, number and sequencing of input data depending on the application being processed. The key point behind reconfigurable architectures is that in some special applications, one such system may replace several ASICs corresponding to different configurations of the former. This replacement clearly results in considerable silicon, power, and weight savings, when ASICs and reconfigurable architectures are contrasted with each other. Reconfigurable architectures, in return, suffer from some performance degradation. This, however, is easily tolerated in many cases. The so-called expensive (i.e. complicated) features of general purpose processors, on the other hand, are not usually exploited thoroughly in our intended applications. Therefore, the major asset of these processors is not utilized efficiently, and hence their application is nearly ruled out, as well. A reconfigurable system may be optimized for multiple applications. Different functions and variable interconnect patterns enable the execution of a range of applications. The combined effect is that applications execute faster (with performance levels close to that of ASICs) and more applications can be executed on the same system. In summary, a reconfigurable architecture lends itself to on-board signal processing, offering small silicon size and physical weight, low power dissipation, and sufficient performance, for many applications. These upsides are useful in many real-world scenarios. Consider a system designed for a given class of applications (image processing, data encryption, etc.). Each application may have a complex and heterogeneous nature and comprises several subtasks with varying characteristics. For instance, a multimedia application may include a data-parallel task, a bitlevel task, irregular computations, high-precision word operations, and a real-time component. For such complex applications with wide-ranging subtasks, the ASIC approach would lead to an uneconomical die size or a large number of separate chips. Also, most general-purpose processors would very likely not satisfy the performance or power constraints for the entire application. However, a reconfigurable system may be optimally reconfigured for each subtask, thus meeting the application constraints within the same chip. The same reconfigurable system can be reused to perform the other tasks in this application class while still satisfying performance and power constraints. In this chapter, first we will discuss the MorphoSys architecture, followed by its first implementation, called the M1 chip. Later, we discuss the application execution model overMorphoSys as a result of the architecture constrains and application characteristics. Then, the compilation framework specifically created to efficient implement application in this type of architectures is described. Finally a brief example of implementing an application onto MorphoSys and its compilation framework is presented. © 2008 Springer.