Fully Dynamic Discrete-Time ΔΣ ADC Using Closed-Loop Two-Stage Cascoded Floating Inverter Amplifiers

Abstract

This brief proposes a fully dynamic discrete-time {Delta }{Sigma } ADC using closed-loop two-stage cascoded floating inverter amplifiers (FIA). The proposed FIA uses a non-cascoded FIA as the 1^{mathrm{ st}} stage and a cascoded one as the 2 ^{mathrm{ nd}}. By using this arrangement as well as applying metal-insulator-metal (MIM) capacitors for floating reservoir capacitors, it stably achieves high gain even with the input common-mode voltage fluctuation without an additional CMFB nor calibrations. The proposed ADC fabricated in a 65nm standard CMOS process realizes a fully dynamic operation without calibration and achieves 88.5dB SNDR, 97.9dB SFDR with an OSR of 256. It consumes 43.5 {mu }text{W} from a 1V supply at a 10MHz sampling frequency.