Hardware-efficient decimation filter design of zero-IF receiver for wireless network

ISSN: 22773878
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The digital scheme realized in this work emphasize on hardware-efficient decimation filter implementation along with their use in the processing of the digitized baseband signal of Zero-Intermediate Frequency (IF) Receiver. This technique allows quick selection of filter coefficients which will yield minimum error in the frequency response characteristics with less hardware complexity in terms of the number of hardware components, especially adders. The overall decimation filter is designed for Digital European Cordless Telephone (DECT) standard specifications. The performance of the entire system is analyzed by counting the number of adders used for each filter coefficient. In this simulation, it is proved that this type of design requires only 15 adders, which is less than 14.2% for droop correction filter and 40% for the Half-band filter.




Srivatsan, K., & Venkatesan, N. (2019). Hardware-efficient decimation filter design of zero-IF receiver for wireless network. International Journal of Recent Technology and Engineering, 8(1), 3044–3048.

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