Design of a cycle-accurate user-retargetable instruction-set simulator using process-based scheduling scheme

Abstract

We designed a cycle-accurate user-retargetable instruction-set simulator (UR-ISS) based on architecture description language (ADL) which is suitable for system-on-chip (SoC) design. It uses a new scheduling method based on process control. It is effective for scheduling multi-cycle instructions and asynchronous events to a pipeline such as interrupts and exceptions frequently found in SoCs. The proposed URISS consists of a byte-code compiler (BCC) and a virtual machine (VM); The BCC translates ADL semantics into byte-codes and the VM executes them. We have investigated that the UR-ISS is 5.5 times faster than HDL models and 2.5 times faster than System-C models on average. We also applied the UR-ISS for CALMRISC32™ during its development and obtained good results for functional validation. © Springer-Verlag 2004.