For static CMOS Clock-Gating is a well-known method to decrease dynamic losses. In order to reduce the static power consumption caused by leakage currents, Power-Gating has been introduced. This paper presents for the first time Clock-Gating and Power-Gating in Adiabatic Logic. As the oscillator signal is both the power and the clock in Adiabatic Logic, a Power-Clock Gating is implemented using a switch to detach the adiabatic logic block from the oscillator. Depending on the technology the optimum switch topology and dimension is discussed. This paper shows that a boosted n-channel MOSFET as well as a transmission gate are good choices as a switch. Adiabatic losses are reduced greatly by shutting down idle adiabatic circuit blocks with Power-Clock Gating. © Springer-Verlag Berlin Heidelberg 2005.
CITATION STYLE
Teichmann, P., Fischer, J., Henzler, S., Amirante, E., & Schmitt-Landsiedel, D. (2005). Power-Clock Gating in adiabatic logic circuits. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 3728 LNCS, pp. 638–646). Springer Verlag. https://doi.org/10.1007/11556930_65
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