Energy, Throughput and Area Evaluation of Regular and Irregular Network on Chip Architectures

Abstract

ABSTARCT Network-on-chip has been proposed in System-on-Chip to achieve high performance, reusability and scalability through generating application specific topologies. Application specific topologies are irregular in structure and take into account certain factors like communication weight, area and energy constraints while building up the topology. Regular topologies like 2D mesh, spidergon are more structured and are built not considering much about the system characteristics and other requirements. Consequently the throughput, power utilization and silicon area vary depending on the topology. This paper provides an evaluation of the performance measures of the regular topological structures and irregular application specific NoC.