Design and verification of CoreConnect™ IP using Esterel

Abstract

This paper explores the practicality of describing and verifying both the hardware and software components of System-on-Chip (SOC) architectures using Esterel. We describe experiments to design and build working hardware based around IBM's CoreConnectTM Intellectual Property (IP) bus. The flow we analyse has been used to produce working hardware realized on Xilinx's FPGAs with soft 32-bit processors. Interesting properties about these systems have been proved by static analysis based on model checking. © Springer-Verlag Berlin Heidelberg 2003.