Am-multiplication: A novel multiplication algorithm based binary multiplexer

Abstract

Multiplication always remain one of the important operation in arithmetic. Researchers have proposed various methods of multiplication using Vedic literature. However, mainly two approaches of arithmetic multiplication, namely, urdhva tiryakbhya and nikhilam sutra from Vedic literature used by many re-searchers for designing binary multiplexer circuit. Such circuits are complex be-cause of large number of electronic components and interconnection overhead. In this work, we proposed a novel multiplication algorithm (am-MULTIPLICATION) for the arithmetic multiplication of two unsigned whole numbers. The algorithm is extended for performing multiplication operation based on binary numerals that is 0 and 1. The proposed algorithm makes use of three sub-algorithm namely MIN, MAX and SUMMATION for calculating the multiplication of unsigned whole numbers based on the equations for developing n number of sets. A circuit is also designed for performing multiplication operation of binary numerals based on serial shift register and carry look-ahead full adder. The simulation of the circuit is presented using software proteus-8, calculated combinational delay is according to VHDL synthesis report.